A global leader in high-speed connectivity and compute silicon for technology infrastructure has announced the release of the industry’s first silicon-proven 3nm Universal Chiplet Interconnect Express (UCIe™) Die-to-Die (D2D) IP subsystem. This breakthrough solution is built on TSMC’s advanced Chip-on-Wafer-on-Substrate (CoWoS®) packaging technology, offering unparalleled performance and innovation in the semiconductor industry.
This comprehensive PHY and controller subsystem, developed through a close collaboration with TSMC, is designed for high-demand applications, including hyperscale data centers, high-performance computing (HPC), and artificial intelligence (AI). Leveraging TSMC’s CoWoS® 2.5D silicon-interposer-based packaging technology, the fully integrated and configurable subsystem delivers a bandwidth density of 8 Tbps/mm while optimizing I/O complexity, power efficiency, and latency.
The subsystem supports various industry protocols—such as PCIe®, CXL™, AXI-4, AXI-S, CXS, and CHI—ensuring broad interoperability within the expanding chiplet ecosystem. It also features live per-lane health monitoring for enhanced system robustness and operates at speeds of 24 Gbps, meeting the bandwidth demands of advanced Die-to-Die (D2D) connectivity.
Following rigorous testing and silicon characterization by TSMC, the UCIe IP subsystem has been validated against UCIe standards under various process conditions (typical, slow, and fast), as well as targeted voltage and temperature settings. The successful validation of the D2D link margin, TXIO, and RXIO loopback margins highlights the readiness of Alphawave Semi’s UCIe IP subsystem for integration into customer SoC designs for next-generation HPC and AI applications.
“Achieving silicon validation of our 3nm 24Gbps UCIe subsystem using TSMC’s advanced packaging marks a key milestone for Alphawave Semi,” said Mohit Gupta, SVP and GM of Custom Silicon and IP at Alphawave Semi. “It sets a new benchmark in high-performance connectivity solutions and demonstrates our expertise in utilizing the TSMC 3DFabric™ ecosystem.”
Dan Kochpatcharin, Head of Ecosystem and Alliance Management Division at TSMC, added, “Our collaboration with Alphawave Semi highlights how we partner with our Open Innovation Platform® (OIP) ecosystem to drive packaging advancements that meet growing AI and HPC application demands.”
Alphawave Semi’s UCIe IP subsystem complies with UCIe Specification Rev 2.0 and includes advanced testability and debug features such as JTAG, BIST, DFT, and Known Good Die (KGD) capabilities. The availability of this 3nm 24Gbps UCIe IP subsystem with TSMC CoWoS® Packaging builds on previous announcements of their standard packaging solution in February 2024 and their first multi-protocol chiplet release in June 2024.
For more information, please visit Alphawave Semi’s website at awavesemi.com.
About Alphawave Semi:
Alphawave Semi is a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure. Their solutions address the growing need for faster, more reliable data transmission with superior performance and lower power consumption. Serving industries such as data centers, AI, 5G, autonomous vehicles, and more, Alphawave Semi continues to push the boundaries of semiconductor innovation. Founded in 2017, the company has rapidly grown by offering cutting-edge IP, custom silicon, and connectivity products to top-tier customers worldwide. For more details, visit awavesemi.com.
